Multi-level Sequential Circuit Partitioning for Delay Minimization of VLSI Circuits
نویسنده
چکیده
Sequential graph partitioning algorithms have been developed to fulfill the requirements of emerging multi-phase problems in circuit delay models. In this paper we propose a heuristic algorithm for kpartition, which minimizes the circuit delay and cut size. Experimental results with MCNC benchmark circuits have shown that the delay in the circuit can be reduced by marginally in comparison with the other algorithms [2,3,11].
منابع مشابه
Multi Objective Inclined Planes System Optimization Algorithm for VLSI Circuit Partitioning
In this paper multi objective optimization problem for partitioning process of VLSI circuit optimization is solved using IPO algorithm. The methodology used in this paper is based upon the dynamic of sliding motion along a frictionless inclined plane. In this work, modules and elements of the circuit are divided into two smaller parts (components) in order to minimize the cutsize and area imbal...
متن کاملAn Automated Algorithm for Partitioning Sequential VLSI Circuits
This paper presents an automated algorithm that partitions large sequential VLSI circuits for pseudoexhaustive testing. The algorithm utilizes the effect of partitioning on hardware overhead, testing time and the delay of critical path. The pseudoexhaustive testing ensures detection of all detectable faults within individual partitions. We have developed an optimization process that can be used...
متن کاملSimultaneous Delay and Power Optimization for Multi-level Partitioning and Floorplanning with Retiming
Delay minimization and power minimization are two important objectives in the design of the high-performance, portable, and wireless computing and communication systems. Retiming is a very effective way for delay optimization for sequential circuits. In this paper we propose a unified framework for multi-level partitioning and floorplanning with retiming, targeting simultaneous delay and power ...
متن کاملPartitioning VLSI Circuits
Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits it is often essential to sub-divide a circuit into smaller parts.Circuit partitioning plays an important role in physical design automation of very large scale integration(VLSI)chips.In VLSI.In VLSI circuit partitioning the problem of obtaining minimum cut is of prime importance.To enhance other criter...
متن کاملStudies on Design for Delay Testability and Delay Test Generation for Sequential Circuits
VLSI (Very Large Scale Integration) circuits are basic components of today’s complex digital systems. In order to realize dependable digital systems, VLSI circuits should be highly reliable. VLSI testing plays an important role in satisfying this requirement. VLSI testing is to check whether faults exist in a circuit, and it consists of two main phases: test generation and test application. In ...
متن کامل